1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly, to a large storage capacity semiconductor memory device operating at high speed with low current consumption.
2. Description of the Background Art
Dynamic random access memory (DRAM) is known as one of semiconductor memory devices. In DRAM, information is stored in a capacitor in an electric charge form, the electric charges stored in the capacitor are read out on a corresponding bit line through an access transistor to be amplified by a sense amplifier circuit for data reading.
In such a DRAM, a memory cell consists of one transistor and one capacitor and therefore, an occupation area thereof is small and a large storage capacity memory can be implemented on a small occupation area.
For the purposes of a high speed operation and reduction in current consumption of a semiconductor memory device and for down-sizing of a processing system in recent years, components of the memory device has been miniaturized. With progress in miniaturization of the elements or components, an area of a memory cell capacitor is also reduced and accordingly, a capacitance value thereof is made smaller. With a smaller capacitance of a memory cell capacitor, an amount of held electric charges is decreased when data of the same voltage level is written to the capacitor. In order to compensate for such a reduction in held electric charge amount, a periodical refresh operation is performed. In the refresh operation, data stored in a memory cell capacitor is read out onto a bit line and then, the data is amplified by a sense amplifier to rewrite the amplified data to the original memory cell capacitor.
Therefore, in a smaller element, when a data retention characteristics is degraded, a refresh interval is required to be shorter in order to compensate for such a degradation of the data retention characteristics. When a refresh interval is made shorter, however, an external processor cannot access the DRAM during a refresh operation, resulting in degradation of performance of the processor.
Furthermore, when a refresh interval is shorter, a current consumed in refresh operations increases. Therefore, it is particularly difficult to meet a low standby current condition required in a data holding mode (for example, a sleep mode) of a battery-powered portable equipment or the like. DRAM with a shorter refresh interval could not be applied to an application such as a battery-powered portable equipment or the like requiring a low current consumption.
A pseudo SRAM (PSRAM), which is DRAM operating like an SRAM (static random access memory), has been known as one of a countermeasure for solving such a refreshing problem associated with DRAM. In PSRAM, to in one cycle in memory access, a cycle of performing an ordinary data write/read and a refresh cycle of performing refresh are continuously performed. Since refresh is performed in one access cycle, the refresh can be hidden from external access, whereby DRAM can be apparently operated as SRAM.
In a case of PSRAM, however, two cycles are required in one access cycle and therefore, a problem that a cycle time cannot be made shorter arises. Especially, in a current fabrication technology at the 0.18 xcexcm level, it is difficult to realize an operating cycle ranging from 70 to 80 nanoseconds (ns), which is required for SRAM.
Configurations for performing refresh independently of external access are disclosed in, for example, Japanese Patent Laying-Open No. 2-21488 (1990), Japanese Patent Laying-Open No. 61-11993 (1986), Japanese Patent Laying-Open No. 55-153194 (1980) and others.
FIG. 50 is a diagram schematically showing a configuration of an array portion of a conventional dynamic type semiconductor memory device. In FIG. 50, normal word lines WL and refresh word lines RWL are provided corresponding to respective rows of memory cells MC. In FIG. 50, there are representatively shown two normal word lines WL0 and WL1, two refresh word lines RWL0 and RWL1, and two memory cells MC0 and MC1. Normal bit lines BL and /BL and refresh bit lines RBL and /RBL are provided corresponding to the memory cell columns.
The memory cells MC (MC0 and MC1) each include: a data access transistor Tr1; a refresh access transistor Tr2; and a capacitor C storing information. A main electrode node (storage node) SN of the capacitor C is coupled commonly to the access transistors Tr1 and Tr2. In the memory cell MC0, the access transistor Tr1 couples the storage node SN to the normal bit line BL in response to a signal on the normal word line WL0, while the refresh access transistor Tr2 connects the storage node SN to the refresh bit line RBL in response to a signal on the refresh word line RWL0.
In the memory cell MC1, the normal access transistor Tr1 connects the storage node SN to the bit line /BL in response to a signal on the normal word line WL1 and the refresh access transistor Tr2 connects the storage node SN to the refresh bit line /RBL in response to a signal on the refresh word line RWL1.
A refresh sense amplifier RSA, which is activated in response to a refresh sense amplifier activating signal xcfx86RSE, is provided to the refresh bit lines RBL and /RBL. A sense amplifier SA, which is activated in response to activation of a sense amplifier activating signal xcfx86SE, is connected to the normal bit lines BL and /BL. The normal bit lines BL and /BL are coupled to an internal data line pair IOP through a column select gate CSG responsive to a column select signal Y.
In the configuration shown in FIG. 50, in an ordinary data access, the normal word line WL (WL0 or WL1) is driven into a selected state. In this case, data stored in the memory cell MC (MC0 or MC1) is read out onto the bit line BL and /BL. Then, the data read out onto the normal bit line BL and /BL is differentially amplified by the (normal) sense amplifier SA. Thereafter, the column select gate CSG is made conductive by the column select signal Y to couple the normal bit lines BL and /BL to the internal data line pair IOP and data write/read is performed.
The refresh word line RWL (RWL0 or RWL1) is driven into a selected state asynchronously with the data access operation. Responsively, a storage data of the memory cell MC (MC0 or MC1) is read out onto the refresh bit lines RBL and /RBL and the memory cell data is differentially amplified and latched by the refresh sense amplifier RSA to then rewrite the data to the original memory cell.
Accordingly, a refresh operation can be internally performed asynchronously with a data access operation and therefore, the refresh operation in the semiconductor memory device can be hidden from an outside, whereby the semiconductor memory device can be accessed independently of an internal refresh cycle.
As shown in FIG. 50, data access and refresh can be performed asynchronously with each other by separately providing the normal bit line pair BL and /BL for performing data access and the refresh bit line pair RBL and /RBL for performing refresh.
However, when refresh and data access are simultaneously in performed on the same memory cell prior to a sense operation, a problem as described below occurs. That is, for example, when the normal word line WL0 and the refresh word line RWL0 are simultaneously driven into a selected state, the capacitor C of the memory cell MC0 is connected to the bit lines BL and RBL through the access transistors Tr1 and Tr2. The bit lines BL and RBL have substantially the same parasitic capacitance with each other. Hence, electric charges stored in the capacitor C are transmitted to the bit lines BL and RBL so as to be distributed thereon. That is, a change in voltage on the bit line is reduced to be, in this case, xc2xd times as large. The sense amplifier SA amplifies a voltage difference (readout voltage) xcex94V between the bit lines BL and /BL as shown in FIG. 51. Hence, when the capacitor C is connected to the bit lines BL and RBL before the sense amplifier SA operates, the readout voltage is xcex94V/2 as shown with a broken line in FIG. 51. Therefore, an operating margin of the sense amplifier SA is smaller and therefore, correct sensing of data cannot be performed.
In a case that the sense amplifiers SA and RSA are simultaneously activated, if memory cell data are read out in reverse directions, a readout voltage is small, and erroneous data reading occurs, according to operating characteristics of the respective sense amplifiers SA and RSA since the sense amplifiers SA and RSA are electrically connected together through the access transistors Tr1 and Tr2 of the memory cell MC0.
In order to avoid such a conflict between a data access operation and a refresh operation, a configuration in which a refresh operation is ceased in data access is disclosed in Japanese Patent Laying-Open No. 2-21488(1990). That is, as shown in FIG. 52, when the normal word line WL is selected, a refresh enable signal /REN is rendered inactive to inhibit a refresh operation for the period till a sense operation on the normal bit lines BL and /BL is completed.
In this case, when data access is performed in advance of refresh, data access can be performed while preventing a data conflict. However, this prior art reference gives no consideration to a case where refresh is performed in advance of data access, followed by the data access. Accordingly, in this case, when refresh is performed in advance, followed by data access, conflict between data cannot be avoided, a readout voltage is smaller, whereby a problem arises that data read and refresh cannot be correctly performed.
It is an object of the present invention to provide a semiconductor memory device capable of reducing a cycle time without lowering data retention characteristics.
It is another object of the present invention to provide a semiconductor memory device capable of performing correct data access without increasing an access time even when refresh and normal row selection are simultaneously performed.
A semiconductor memory device according to the present invention includes: a plurality of memory cells arranged in rows and columns; a plurality of normal bit line pairs each provided corresponding to the respective memory cell columns, and each having memory cells on a corresponding column connected thereto, each bit line pair having first and second normal bit lines; and a plurality of refresh bit line pairs provided correspondingly to the respective memory cell columns, and each having memory cells on a corresponding column connected thereto, each bit line having first and second refresh bit lines. Each of the plurality of memory cells includes: a first transistor connected between one of the first and second normal bit lines of a corresponding normal bit line pair and a storage node; and a second transistor connected between the storage node and one of the first and second refresh bit lines of the corresponding column.
A semiconductor memory device according to the present invention further includes: a plurality of normal word lines, provided corresponding to respective rows of memory cells, each having first transistors of memory cells on a corresponding row connected thereto; a plurality of refresh word lines, provided correspondingly to respective rows of memory cells, each having second transistors of memory cells on a corresponding row connected thereto; a refresh row select circuit for selecting a refresh word line, specified according to a refresh address, of the plurality of refresh to word lines; a normal row select circuit for selecting a normal word line specified according to an external address, of the plurality of normal word lines,; a determining circuit for determining coincidence/non-coincidence between the refresh address and the external address; a comparator for comparing activation timings of a refresh requesting signal and a memory cell select cycle start instructing signal; and access circuitry for performing data access through a refresh bit line pair when the determining circuit detects coincidence and the comparator indicates that activation of said refresh requesting signal is earlier.
In a case where a refresh address and an external address specify the same row, when the refresh request is activated earlier, data access is made through a refresh bit line pair. Thus, it is not necessary to defer data access, and data access (data write/read) can be performed at high speed, even if arbitration is performed between a refresh operation and a data access operation.
Furthermore, since a refresh operation is performed asynchronously with an external access, an external device can perform data access at high speed without considering the refresh operation, thereby enabling construction of a high speed processing system.